ae5fa08abd
The cards affected include the TE131/3, TE235/435, A4B, and A8B. Update all PCIe cards' firmware to increase the incoming and outgoing TDM FIFOs to 16ms. The FIFOs will only be filled to a depth equal to the driver's latency setting (ie. 3ms default). The total system latency is not effected. The firmware and driver now also report the maximum DMA transaction time when in DEBUG mode to aid in determining if the system is experiencing long PCIe transactions (ie. TLP completion timeouts). Decreased the maximum latency to from 20 to 12ms Signed-off-by: Russ Meyerriecks <rmeyerriecks@digium.com>
205 lines
5.4 KiB
C
205 lines
5.4 KiB
C
/*
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* wcxb SPI library
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*
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* Copyright (C) 2013 Digium, Inc.
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*
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* All rights reserved.
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*
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*/
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/*
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* See http://www.asterisk.org for more information about
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* the Asterisk project. Please do not directly contact
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* any of the maintainers of this project for assistance;
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* the project provides a web site, mailing lists and IRC
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* channels for your use.
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*
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* This program is free software, distributed under the terms of
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* the GNU General Public License Version 2 as published by the
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* Free Software Foundation. See the LICENSE file included with
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* this program for more details.
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*/
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#ifndef __WCXB_H__
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#define __WCXB_H__
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#define WCXB_DEFAULT_LATENCY 3U
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#define WCXB_DEFAULT_MAXLATENCY 12U
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#define WCXB_DMA_CHAN_SIZE 128
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
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/* The is_pcie member was backported but I'm not sure in which version. */
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# ifndef RHEL_RELEASE_VERSION
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#define WCXB_PCI_DEV_DOES_NOT_HAVE_IS_PCIE
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# endif
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#else
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#endif
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struct wcxb;
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struct wcxb_operations {
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void (*handle_receive)(struct wcxb *xb, void *frame);
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void (*handle_transmit)(struct wcxb *xb, void *frame);
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void (*handle_error)(struct wcxb *xb);
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void (*handle_interrupt)(struct wcxb *xb, u32 pending);
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};
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struct wcxb_meta_desc;
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struct wcxb_hw_desc;
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/**
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* struct wcxb - Interface to wcxb firmware.
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* @last_retry_count: Running count of times firmware had to retry host DMA
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* transaction. Debugging aide.
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*/
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struct wcxb {
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struct pci_dev *pdev;
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spinlock_t lock;
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const struct wcxb_operations *ops;
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unsigned int *debug;
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unsigned int max_latency;
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unsigned int latency;
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struct {
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u32 have_msi:1;
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u32 latency_locked:1;
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u32 drive_timing_cable:1;
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#ifdef WCXB_PCI_DEV_DOES_NOT_HAVE_IS_PCIE
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u32 is_pcie:1;
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#endif
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u32 dma_ins:1;
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} flags;
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void __iomem *membase;
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struct wcxb_meta_desc *meta_dring;
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struct wcxb_hw_desc *hw_dring;
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unsigned int dma_head;
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unsigned int dma_tail;
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dma_addr_t hw_dring_phys;
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struct dma_pool *pool;
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unsigned long framecount;
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#ifdef DEBUG
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u8 last_retry_count;
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u8 max_retry_count;
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u32 last_dma_time;
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u32 max_dma_time;
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#endif
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};
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extern int wcxb_init(struct wcxb *xb, const char *board_name, u32 int_mode);
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extern void wcxb_release(struct wcxb *xb);
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extern int wcxb_start(struct wcxb *xb);
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extern void wcxb_stop(struct wcxb *xb);
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extern int wcxb_wait_for_stop(struct wcxb *xb, unsigned long timeout_ms);
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extern bool wcxb_is_stopped(struct wcxb *xb);
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enum wcxb_clock_sources {
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WCXB_CLOCK_SELF, /* Use the internal oscillator for timing. */
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WCXB_CLOCK_RECOVER, /* Recover the clock from a framer. */
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#ifdef RPC_RCLK
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WCXB_CLOCK_RECOVER_ALT, /* Recover the clock from a framer. */
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#endif
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WCXB_CLOCK_SLAVE /* Recover clock from any timing header. */
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};
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extern enum wcxb_clock_sources wcxb_get_clksrc(struct wcxb *xb);
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extern void wcxb_set_clksrc(struct wcxb *xb, enum wcxb_clock_sources clksrc);
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static inline void wcxb_enable_timing_header_driver(struct wcxb *xb)
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{
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xb->flags.drive_timing_cable = 1;
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}
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static inline bool wcxb_is_timing_header_driver_enabled(struct wcxb *xb)
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{
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return 1 == xb->flags.drive_timing_cable;
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}
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static inline void wcxb_disable_timing_header_driver(struct wcxb *xb)
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{
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xb->flags.drive_timing_cable = 0;
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}
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enum wcxb_reset_option {
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WCXB_RESET_NOW,
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WCXB_RESET_LATER
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};
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extern u32 wcxb_get_firmware_version(struct wcxb *xb);
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extern int wcxb_check_firmware(struct wcxb *xb, const u32 expected_version,
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const char *firmware_filename,
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bool force_firmware,
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enum wcxb_reset_option reset);
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extern void wcxb_stop_dma(struct wcxb *xb);
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extern void wcxb_disable_interrupts(struct wcxb *xb);
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static inline void wcxb_gpio_set(struct wcxb *xb, u32 bits)
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{
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u32 reg;
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unsigned long flags;
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spin_lock_irqsave(&xb->lock, flags);
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reg = ioread32be(xb->membase);
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iowrite32be(reg | bits, xb->membase);
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spin_unlock_irqrestore(&xb->lock, flags);
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}
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static inline void wcxb_gpio_clear(struct wcxb *xb, u32 bits)
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{
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u32 reg;
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unsigned long flags;
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spin_lock_irqsave(&xb->lock, flags);
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reg = ioread32be(xb->membase);
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iowrite32be(reg & (~bits), xb->membase);
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spin_unlock_irqrestore(&xb->lock, flags);
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}
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static inline void
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wcxb_set_maxlatency(struct wcxb *xb, unsigned int max_latency)
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{
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unsigned long flags;
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spin_lock_irqsave(&xb->lock, flags);
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xb->max_latency = clamp(max_latency,
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xb->latency,
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WCXB_DEFAULT_MAXLATENCY);
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spin_unlock_irqrestore(&xb->lock, flags);
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}
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static inline void
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wcxb_set_minlatency(struct wcxb *xb, unsigned int min_latency)
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{
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unsigned long flags;
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spin_lock_irqsave(&xb->lock, flags);
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xb->latency = clamp(min_latency, WCXB_DEFAULT_LATENCY,
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WCXB_DEFAULT_MAXLATENCY);
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spin_unlock_irqrestore(&xb->lock, flags);
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}
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static inline void
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wcxb_lock_latency(struct wcxb *xb)
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{
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unsigned long flags;
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spin_lock_irqsave(&xb->lock, flags);
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xb->flags.latency_locked = 1;
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spin_unlock_irqrestore(&xb->lock, flags);
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return;
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}
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static inline void
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wcxb_unlock_latency(struct wcxb *xb)
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{
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unsigned long flags;
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spin_lock_irqsave(&xb->lock, flags);
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xb->flags.latency_locked = 0;
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spin_unlock_irqrestore(&xb->lock, flags);
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return;
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}
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/* Interface for the echocan block */
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extern void wcxb_enable_echocan(struct wcxb *xb);
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extern void wcxb_disable_echocan(struct wcxb *xb);
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extern void wcxb_reset_echocan(struct wcxb *xb);
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extern void wcxb_enable_echocan_dram(struct wcxb *xb);
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extern bool wcxb_is_echocan_present(struct wcxb *xb);
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extern u16 wcxb_get_echocan_reg(struct wcxb *xb, u32 address);
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extern void wcxb_set_echocan_reg(struct wcxb *xb, u32 address, u16 val);
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#endif
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