8d29ecb783
If the DSP ever finds it's way into a bad state it can be possible for a timeslot to get 'wedged'. All attempts to create a channel in a wedged timeslot will fail and the WARN_ON macro can quickly fill the logs. This change adds some more debugging information (which timeslot is wedged) along with the result code from the DSP and puts it all behind a printk_ratelimit. Signed-off-by: Shaun Ruffell <sruffell@digium.com> Acked-by: Kinsey Moore <kmoore@digium.com> Acked-by: Russ Meyerriecks <rmeyerriecks@digium.com> git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@9437 a0bf4364-ded3-4de4-8d8a-66a801d63aff |
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