476 lines
14 KiB
Perl
Executable File
476 lines
14 KiB
Perl
Executable File
#! /usr/bin/perl -w
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use strict;
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# Make warnings fatal
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local $SIG{__WARN__} = sub { die @_ };
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#
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# $Id$
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#
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#
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# Written by Oron Peled <oron@actcom.co.il>
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# Copyright (C) 2006, Xorcom
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#
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# All rights reserved.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# See the file LICENSE in the top level of this tarball.
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#
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# This script is run from the xpp kernel module upon detection
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# of a new XPD.
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#
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# Expects the following environment variables to be set:
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# XBUS_NAME - bus name
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# UNIT_NUMBER - xpd unit number
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# UNIT_SUBUNITS - number of subunits in this xpd
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# UNIT_TYPE - xpd type number (from protocol reply):
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# 1 - FXS
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# 2 - FXO
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# 3 - BRI
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# 4 - PRI
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# XBUS_REVISION - xbus revision number
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# XBUS_CONNECTOR - xbus connector string
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#
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# Output data format:
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# - An optional comment start with ';' or '#' until the end of line
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# - Optional Blank lines are ignored
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# - Fields are whitespace separated (spaces or tabs)
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#
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# The fields are (in command line order):
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# 1. CHIP select in decimal (ignored, taken from 3 LSB's of subunit number)
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# 2. Command word:
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# - RD Read Direct register.
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# - RS Read Sub-register.
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# - WD Write Direct register.
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# - WS Write Sub-register.
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# 3. Register number in hexadecimal.
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# 4. Subregister number in hexadecimal. (for RS and WS commands).
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# 5. Data byte in hexadecimal. (for WD and WS commands only).
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#
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package main;
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use File::Basename;
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use Getopt::Std;
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my $program = basename("$0");
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my $init_dir = dirname("$0");
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BEGIN { $init_dir = dirname($0); unshift(@INC, "$init_dir"); }
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use XppConfig $init_dir;
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my $unit_id;
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my %opts;
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getopts('o:', \%opts);
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my %settings;
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sub logit {
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print STDERR "$unit_id: @_\n";
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}
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sub debug {
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logit @_ if $settings{debug};
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}
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# Arrange for error logging
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if (-t STDERR) {
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$unit_id = 'Interactive';
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debug "Interactive startup";
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} else {
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$unit_id = "$ENV{XBUS_NAME}/UNIT-$ENV{UNIT_NUMBER}";
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open (STDERR, "| logger -t $program -p kern.info") || die;
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debug "Non Interactive startup";
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foreach my $k (qw(
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XBUS_NAME
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XBUS_NUMBER
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UNIT_NUMBER
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UNIT_TYPE
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UNIT_SUBUNITS
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UNIT_SUBUNITS_DIR
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XBUS_REVISION
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XBUS_CONNECTOR
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XBUS_LABEL)) {
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unless(defined $ENV{$k}) {
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logit "Missing ENV{$k}\n";
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die;
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}
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}
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}
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sub select_subunit($) {
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my $subunit = shift;
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die unless defined $subunit;
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my $output;
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if($opts{o}) {
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$output = $opts{o};
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} else {
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$output = sprintf "/sys/bus/xpds/devices/%02d:%1d:%1d/chipregs",
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$ENV{XBUS_NUMBER}, $ENV{UNIT_NUMBER}, $subunit;
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if(! -f $output) {
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my $xpd_name = sprintf("XPD-%1d%1d", $ENV{UNIT_NUMBER}, $subunit);
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$output = "/proc/xpp/$ENV{XBUS_NAME}/$xpd_name/chipregs";
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logit "OLD DRIVER: does not use /sys chipregs. Falling back to /proc"
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if -f $output;
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}
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}
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open(REG, ">$output") || die "Failed to open '$output': $!\n";
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my $oldfh = select REG;
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print "# Selecting subunit $subunit\n" if $opts{o};
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return $oldfh;
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}
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package BRI;
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sub gen {
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my $fmt = shift;
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$| = 1;
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printf "$fmt\n", @_;
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}
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# Turning on/off multi-byte packet reception.
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sub multibyte($) {
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my $active = (shift) ? 'M' : 'm';
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for my $subunit (0 .. $ENV{UNIT_SUBUNITS} - 1) {
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#main::logit "multibyte(): $subunit -> $active";
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main::select_subunit($subunit);
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BRI::gen "$subunit W$active";
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}
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}
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sub read_defaults() {
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if(XppConfig::read_config(\%settings)) {
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main::logit "Defaults from $settings{xppconf}";
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} else {
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main::logit "No defaults file, use hard-coded defaults.";
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}
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}
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package BRI::Port;
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sub new {
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my $pack = shift;
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my $port = { @_ };
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bless $port, $pack;
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}
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# zap_xhfc_su.c:995
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sub init_su {
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my $port = shift;
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my $portnum = $port->{PORT_NUM};
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my $port_mode_up = $port->{PORT_MODE_UP};
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my $port_mode_exch = $port->{PORT_MODE_EXCH};
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my $bri_nt = $port->{BRI_NT};
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#main::logit "init_su(portnum=$portnum, port_mode_up=$port_mode_up, bri_nt=$bri_nt)";
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# Setting PLL
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# R_PLL_CTRL = 0 (V_PLL_M = 0, Reset PLL, Disable PLL_
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# R_CLK_CFG = 05 (PLL clock as system clock, output it to CLK_OUT pin)
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# R_PLL_P = 1
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# R_PLL_N = 6
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# R_PLL_S = 1
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# R_PLL_CTRL = 1 (V_PLL_M)
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BRI::gen "#--------------------------- init_su($portnum, $bri_nt, $port_mode_up, $port_mode_exch)";
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BRI::gen "$portnum WD 02 04";
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BRI::gen "$portnum WD 50 00"; # disable PLL
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BRI::gen "$portnum WD 51 02";
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BRI::gen "$portnum WD 52 06";
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BRI::gen "$portnum WD 53 04";
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BRI::gen "$portnum WD 50 01"; # Enable PLL
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BRI::gen "$portnum WD 02 05"; # Enable PLL
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su_sel($portnum); # select port
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if ("$port_mode_up" == 1) {
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$port->{CTRL3} = 0x01; # A_ST_CTRL3: V_ST_SEL = 1
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$port->{CTRL0} = 0x10; # A_SU_CTRL0: V_ST_SQ_EN = 1
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BRI::gen "$portnum WD 34 0F"; # A_MS_TX:
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# (multiframe/superframe transmit register)
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} else {
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$port->{CTRL3} = 0x00; # A_ST_CTRL3: V_ST_SEL = 0
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$port->{CTRL0} = 0x00; # A_SU_CTRL0: V_ST_SQ_EN = 0
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}
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if ("$bri_nt" == 1) {
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$port->{CTRL0} |= 0x04; # V_SU_MD
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}
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# ((V_SU_EXCH)?0x80:00) (change polarity)
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if($port_mode_exch) {
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$port->{CTRL2} = 0x80;
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} else {
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$port->{CTRL2} = 0x00;
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}
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BRI::gen "$portnum WD 35 %02X", $port->{CTRL3}; # A_ST_CTRL3
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BRI::gen "$portnum WD 31 %02X", $port->{CTRL0}; # A_SU_CTRL0
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BRI::gen "$portnum WD 35 F8"; # A_ST_CTRL3 = set end of pulse control to 0xF8
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BRI::gen "$portnum WD 32 09"; # A_SU_CTRL1 = Ignore E-channel data, Force automatic transition from G2 to G3
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BRI::gen "$portnum WD 33 %02X", $port->{CTRL2}; # A_SU_CTRL2
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# zap_xhfc_su.c:1030 in init_su()
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# A_SU_CLK_DLY
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my $clk_dly;
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if ("$bri_nt" == 1) {
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$clk_dly = 0x6C;
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} else {
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$clk_dly = 0x0E;
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}
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#main::logit "clk_dly=$clk_dly";
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BRI::gen "$portnum WD 37 %02X", "$clk_dly";
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}
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sub su_sel {
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if (@_ != 1 ) {
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main::logit "ERROR: su_sel() called with " . scalar(@_) . " parameters";
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exit 1;
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}
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my $portnum = shift;
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BRI::gen "$portnum WD 16 %02X", $portnum; # R_SU_SEL
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}
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# zap_xhfc_su.c:281
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sub xhfc_selfifo {
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my $port = shift;
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my $portnum = $port->{PORT_NUM};
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if (@_ != 1 ) {
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main::logit "ERROR: xhfc_selfifo() called with " . scalar(@_) . " parameters";
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exit 1;
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}
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my $fifonum = shift;
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#main::logit "xhfc_selfifo($fifonum)";
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BRI::gen "$portnum WD 0F %02X", $fifonum;
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# --> WAIT UNTIL (R_STATUS & M_BUSY) == 0
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}
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# zap_xhfc_su.c:295
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sub xhfc_resetfifo() {
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my $port = shift;
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my $portnum = $port->{PORT_NUM};
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#main::logit "xhfc_resetfifo()";
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# A_INC_RES_FIFO = M_RES_FIFO | M_RES_FIFO_ERR
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BRI::gen "$portnum WD 0E 0A";
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# --> WAIT UNTIL (R_STATUS & M_BUSY) == 0
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}
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# zap_xhfc_su.c:1040
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# Initialize fifo (called for each portnum, channel, direction)
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sub setup_fifo {
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my $port = shift;
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my $chan = shift;
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my $direction = shift;
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my $conhdlc = shift;
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my $subcfg = shift;
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my $fifoctrl = shift;
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my $portnum = $port->{PORT_NUM};
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my $port_mode_up = $port->{PORT_MODE_UP};
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my $port_mode_exch = $port->{PORT_MODE_EXCH};
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my $bri_nt = $port->{BRI_NT};
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BRI::gen "#--------------------------- setup_fifo($portnum, $chan, $direction)";
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# my $fifonum = 0x80 | ($portnum << 3) | ($chan << 1) | ($direction); # # MSB first
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my $fifonum = ($portnum << 3) | ($chan << 1) | ($direction); # # MSB first
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my $r_slot = ($portnum << 3) | ($chan << 1) | ($direction);
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# channel order workaround, swap odd and even portnums in $r_slot for PCM (chan 0, 1) only
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if ("$chan" == 0 || "$chan" == 1) {
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$r_slot = $r_slot ^ 0x08;
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}
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my $short_portnum = $portnum & 0x03;
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my $a_sl_cfg = (0x80 | ($short_portnum << 3) | ($chan << 1) | ($direction)); # receive data from STIO2, transmit to STIO1
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#main::logit "setup_fifo($fifonum)";
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$port->xhfc_selfifo($fifonum);
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# A_CON_HDLC: transparent mode selection
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BRI::gen "$portnum WD FA %02X", $conhdlc;
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# A_SUBCH_CFG: subchnl params
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BRI::gen "$portnum WD FB %02X", $subcfg;
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# A_FIFO_CTRL: FIFO Control Register
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BRI::gen "$portnum WD FF %02X", $fifoctrl;
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$port->xhfc_resetfifo();
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$port->xhfc_selfifo($fifonum); # wait for busy is builtin in this command
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BRI::gen "$portnum WD 10 %02X", $r_slot; # R_SLOT
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BRI::gen "$portnum WD D0 %02X", $a_sl_cfg; # A_SL_CFG
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#system("/bin/echo \"----=====TE\" \"short_portnum=\"$short_portnum \"portnum=\" $portnum \"chan=\" $chan\"======----\n\" >>/root/xortel/test_init");
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}
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# zap_xhfc_su.c:1071
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sub setup_su {
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my $port = shift;
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my $bchan = shift;
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my $portnum = $port->{PORT_NUM};
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my $port_mode_exch = $port->{PORT_MODE_EXCH};
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my $bri_nt = $port->{BRI_NT};
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BRI::gen "#--------------------------- setup_su($portnum, $bchan)";
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#main::logit "setup_su(portnum=$portnum, bchan=$bchan, port_mode_exch=$port_mode_exch, bri_nt=$bri_nt)";
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$port->{CTRL0} |= (1 << $bchan) | $bri_nt;
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$port->{CTRL2} |= ($port_mode_exch << 7) | (1 << $bchan);
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su_sel($portnum); # Select port
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BRI::gen "$portnum WD 31 %02X", $port->{CTRL0}; # A_SU_CTRL0: V_B1_TX_EN | V_SU_MD | (NT/TE)
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BRI::gen "$portnum WD 33 %02X", $port->{CTRL2}; # A_SU_CTRL2: V_B1_RX_EN
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}
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sub xhfc_ph_command {
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my $port = shift;
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my $cmd = shift;
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my $portnum = $port->{PORT_NUM};
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#main::logit "xhfc_ph_command(portnum=$portnum)";
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if ("$cmd" eq "HFC_L1_ACTIVATE_TE") {
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su_sel($portnum); # Select port
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BRI::gen "$portnum WD 30 60"; # A_SU_WR_STA = (M_SU_ACT & 0x03)
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# (set activation)
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} elsif ("$cmd" eq "HFC_L1_FORCE_DEACTIVATE_TE") {
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su_sel($portnum); # Select port
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BRI::gen "$portnum WD 30 40"; # A_SU_WR_STA = (M_SU_ACT & 0x02)
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# (set deactivation)
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} elsif ("$cmd" eq "HFC_L1_ACTIVATE_NT") {
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su_sel($portnum); # Select port
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BRI::gen "$portnum WD 30 E0"; # A_SU_WR_STA = (M_SU_ACT & 0x03) | 0x80
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# (set activation + NT)
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} elsif ("$cmd" eq "HFC_L1_DEACTIVATE_NT") {
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su_sel($portnum); # Select port
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BRI::gen "$portnum WD 30 40"; # A_SU_WR_STA = (M_SU_ACT & 0x02)
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# (set deactivation)
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}
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}
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sub zthfc_startup {
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my $port = shift;
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my $portnum = $port->{PORT_NUM};
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my $port_mode_exch = $port->{PORT_MODE_EXCH};
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my $bri_nt = $port->{BRI_NT};
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#main::logit "zthfc_startup(portnum=$portnum, port_mode_exch=$port_mode_exch, bri_nt=$bri_nt)";
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# PCM <-> ST/Up Configuration
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foreach my $chan ( 0, 1 ) {
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$port->setup_fifo($chan, 0, 0xFE, 0, 0);# Transparent mode, FIFO EN, ST->PCM
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$port->setup_fifo($chan, 1, 0xFE, 0, 0);# Transparent mode, FIFO EN, ST->PCM
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$port->setup_su($chan); # zap_xhfc_su.c:194
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}
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# Dahdi chan 2 used as HDLC D-Channel
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$port->setup_fifo(2, 0, 0x05, 2, 0); # D-TX: zap_xhfc_su.c:205
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$port->setup_fifo(2, 1, 0x05, 2, 0); # D-RX: zap_xhfc_su.c:206
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# E-chan, Echo channel is ignored
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# enable this port's state machine
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su_sel($portnum); # Select port
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# A_SU_WR_STA: reset port state machine
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BRI::gen "$portnum WD 30 00";
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if ("$bri_nt" == 0) {
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$port->xhfc_ph_command("HFC_L1_ACTIVATE_TE");
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} else {
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$port->xhfc_ph_command("HFC_L1_ACTIVATE_NT");
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}
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}
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package main;
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debug "Starting '$0'";
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BRI::read_defaults;
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#------------------------------------------- Instance detection
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# zap_xhfc_su.c:895
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sub init_xhfc($) {
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my $portnum = shift;
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main::debug "init_xhfc($portnum)";
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BRI::gen "#--------------------------- init_xhfc";
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BRI::gen "$portnum WD 0D 00"; # r_FIFO_MD: 16 fifos,
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# 64 bytes for TX and RX each (FIFO mode config)
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# software reset to enable R_FIFO_MD setting
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BRI::gen "$portnum WD 00 08"; # R_CIRM = M_SRES (soft reset)
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# --> WAIT 5u
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BRI::gen "$portnum WD 00 00"; # R_CIRM = 0 (zero it to deactivate reset)
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# amplitude
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BRI::gen "$portnum WD 46 80"; # R_PWM_MD: (PWM output mode register)
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# PWM push to zero only
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BRI::gen "$portnum WD 39 18"; # R_PWM1: (modulator register for PWM1)
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# set duty cycle
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BRI::gen "$portnum WD 0C 11"; # R_FIFO_THRES: (FIFO fill lvl control register)
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# RX/TX threshold = 16 bytes
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# set PCM bus mode to slave by default
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BRI::gen "$portnum WD 14 08"; # R_PCM_MD0 = PCM slave mode, F0IO duration is 2 HFC_PCLK's
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# (C4IO, F0IO are inputs)
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BRI::gen "$portnum WD 14 98"; # R_PCM_MD0: Index value to select
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# the register at address 15
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BRI::gen "$portnum WD 15 20"; # R_PCM_MD1: V_PLL_ADJ (DPLL adjust speed),
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# in the last slot of PCM frame
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# V_PCM_DR, C4IO is 16.384MHz(128 time slots)
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BRI::gen "$portnum WD 4C 07"; # GPIOGPIO function (not PWM) on GPIO0, GPIO1 and GPIO2 pins
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BRI::gen "$portnum WD 4A 07"; # Output enable for GPIO0, GPIO1 and GPIO2 pins
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BRI::gen "$portnum WD 48 01"; # GPIO output data bits
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}
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my @port_type = (
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{ 'BRI_NT' => 1 },
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{ 'BRI_NT' => 0 }
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);
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# zap_xhfc_su.c:175
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sub main() {
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my $subunit;
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my $subunits_mask = pack("C", $ENV{UNIT_SUBUNITS_DIR});
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my @direction = split(//, unpack("b*", $subunits_mask));
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#logit "main(): UNIT_TYPE=$ENV{UNIT_TYPE} UNIT_SUBUNITS_DIR=[@direction]";
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if(!$opts{o}) {
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foreach my $var (qw(XBUS_NAME UNIT_NUMBER UNIT_TYPE UNIT_SUBUNITS UNIT_SUBUNITS_DIR XBUS_REVISION XBUS_CONNECTOR)) {
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die "Missing mandatory '$var' environment variable" unless defined $var;
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}
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}
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# Turn off multi-byte packet reception before initialization started
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# Otherwise we mess with registers while the FPGA firmware tries to
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# send us packets.
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BRI::multibyte(0);
|
|
|
|
# Port initialization
|
|
for($subunit = 0; $subunit < $ENV{UNIT_SUBUNITS}; $subunit++) {
|
|
my $is_nt = $direction[$subunit];
|
|
|
|
main::select_subunit($subunit);
|
|
if(($subunit % 4) == 0) { # A new xhfc chip
|
|
#logit "main(): Initializing chip";
|
|
init_xhfc($subunit); # zap_xhfc_su.c:1173 in setup_instance()
|
|
}
|
|
#logit "main(): Initializing subunit $subunit is_nt=$is_nt";
|
|
my $p = BRI::Port->new(
|
|
'PORT_NUM' => $subunit,
|
|
'BRI_NT' => $is_nt,
|
|
'PORT_MODE_UP' => 0,
|
|
'PORT_MODE_EXCH' => 0
|
|
);
|
|
# zap_XHfc_su.c:1186 in setup_instance()
|
|
$p->init_su;
|
|
$p->zthfc_startup;
|
|
}
|
|
# Turn on multi-byte packet reception when ports initialization finished
|
|
BRI::multibyte(1);
|
|
}
|
|
|
|
main;
|
|
|
|
debug "Ending '$0'";
|
|
|
|
close REG;
|
|
close STDERR;
|
|
exit 0;
|