* We need to split the BRI D-Channel (HDLC) frames to smaller packets,
limitation of the FPGA.
* This changes batches BRI D-channel packets of the same HDLC frame to a
single XPP frame.
* Avoids an accidental fragmantion in case we were delayed for a few ms-s.
* Also improves efficiency.
Signed-off-by: Oron Peled <oron.peled@xorcom.com>
Acked-By: Tzafrir Cohen <tzafrir.cohen@xorcom.com>
git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@10390 a0bf4364-ded3-4de4-8d8a-66a801d63aff
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