bf3fe05dfb
This needs some more testing before it's on by default. If the card is otherwise functioning, these messages may be confusing to the user. If the card is not functioning, the driver can be reloaded with debug to check for this condition. Signed-off-by: Shaun Ruffell <sruffell@digium.com> git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@9205 a0bf4364-ded3-4de4-8d8a-66a801d63aff
187 lines
6.0 KiB
C
187 lines
6.0 KiB
C
/*
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* Tormenta 2 Quad-T1 PCI Driver
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*
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* Written by Mark Spencer <markster@linux-suppot.net>
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*
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* Copyright (C) 2001 Jim Dixon / Zapata Telephony.
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* Copyright (C) 2001-2008, Digium, Inc.
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*
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* All rights reserved.
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*
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*/
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/*
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* See http://www.asterisk.org for more information about
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* the Asterisk project. Please do not directly contact
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* any of the maintainers of this project for assistance;
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* the project provides a web site, mailing lists and IRC
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* channels for your use.
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*
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* This program is free software, distributed under the terms of
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* the GNU General Public License Version 2 as published by the
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* Free Software Foundation. See the LICENSE file included with
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* this program for more details.
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*/
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#ifndef _TOR2_HW_H
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#define _TOR2_HW_H
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/*
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* The Tormenta two consists of the following block architecture:
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*
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* [ Spartan ] --- [ DS 21Q352 ] -- Xfrms -- Span 1
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* | | | | | | |
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* Local Bus +----- Span 2
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* | | | |
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* [ PCI 9030 ] +----- Span 3
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* | | | | | |
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* PCI BUS +----- Span 4
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*
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* All communicatiosn to the framer (21Q352) are performed
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* through the PCI 9030 part using memory mapped I/O.
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*
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* The Tormenta 2 requires a 2 2k wondows memory space
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* which is mapped as follows:
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*
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* First (32 bit) space:
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*
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* 0x0000 -> 0x07FF: Memory map of Tx and Rx buffers. They are stored
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* with increasing channel number, with each span in
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* a byte of a 32-bit long word:
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* Bits 31-24: Span 1
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* Bits 23-16: Span 2
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* Bits 16- 8: Span 3
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* Bits 7- 0: Span 4
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*
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*
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* Second (8 bit) space:
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*
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* 0x0000 -> 0x00FF: Registers for Transceiver 1
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* 0x0100 -> 0x01FF: Registers for Transceiver 2
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* 0x0200 -> 0x02FF: Registers for Transceiver 3
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* 0x0300 -> 0x03FF: Registers for Transceiver 4
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*
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* 0x400 Write -> Firmware load location for Xilinx. This is the only valid
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* register until the Xilinx is programmed to decode
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* the remainder!
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*
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* 0x400 Write -> clkreg (sync source)
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* 0=free run, 1=span 1, 2=span 2, 3=span 3, 4=span 4.
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*
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* 0x400 Read -> statreg
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* bit 0 - Interrupt Enabled
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* bit 1 - Interrupt Active
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* bit 2 - Dallas Interrupt Active
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*
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* 0x401 Write -> ctlreg as follows:
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* bit 0 - Interrupt Enable
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* bit 1 - Drives "TEST1" signal ("Interrupt" outbit)
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* bit 2 - Dallas Interrupt Enable (Allows DINT signal to drive INT)
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* bit 3 - External Syncronization Enable (MASTER signal).
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* bit 4 - Select E1 Divisor Mode (0 for T1, 1 for E1).
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* bit 5 - Remote serial loopback (When set to 1, TSER is driven from RSER)
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* bit 6 - Local serial loopback (When set to 1, Rx buffers are driven from Tx buffers)
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* bit 7 - Interrupt Acknowledge (set to 1 to acknowledge interrupt)
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*
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* 0x402 Write -> LED register as follows:
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* bit 0 - Span 1 Green
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* bit 1 - Span 1 Red
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* bit 2 - Span 2 Green
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* bit 3 - Span 2 Red
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* bit 4 - Span 3 Green
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* bit 5 - Span 3 Red
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* bit 6 - Span 4 Green
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* bit 7 - Span 4 Red
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* NOTE: turning on both red and green yields yellow.
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*
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* 0x403 Write -> TEST2, writing to bit 0 drives TEST2 pin.
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*
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* 0x404 Write -> ctlreg1 as follows:
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* bit 0 - Non-REV.A Mode (Set this bit for Dallas chips later then Rev. A)
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*/
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#ifdef NEED_PCI_IDS
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/*
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* Provide routines for identifying a tormenta card
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*/
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#define PCI_VENDOR_ID_PLX 0x10b5
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#ifdef __KERNEL__
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static struct pci_device_id tor2_pci_ids[] =
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#else
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#define PCI_ANY_ID -1
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static struct tor2_pci_id {
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int vendor;
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int device;
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int subvendor;
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int subdevice;
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int class;
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int classmask;
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unsigned long driver_data;
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} tor2_pci_ids[] =
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#endif /* __KERNEL__ */
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{
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{ PCI_VENDOR_ID_PLX, 0x9030, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long)"PLX 9030" }, /* PLX 9030 Development board */
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{ PCI_VENDOR_ID_PLX, 0x3001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long)"PLX Development Board" }, /* PLX 9030 Development board */
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{ PCI_VENDOR_ID_PLX, 0xD00D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long)"Tormenta 2 Quad T1/PRI or E1/PRA" }, /* Tormenta 2 */
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{ PCI_VENDOR_ID_PLX, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long)"Tormenta 2 Quad T1/E1 (non-Digium clone)" }, /* Tormenta 2 clone */
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{ 0, }
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};
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#ifndef __KERNEL__
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/* We provide a simple routine to match the given ID's */
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static inline int tor2_pci_match(int vendorid, int deviceid, char **variant)
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{
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/* Returns 1 if this is a tormenta card or 0 if it isn't */
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int x;
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for (x = 0; x< sizeof(tor2_pci_ids) / sizeof(tor2_pci_ids[0]); x++)
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if (((tor2_pci_ids[x].vendor == PCI_ANY_ID) ||
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(tor2_pci_ids[x].vendor == vendorid)) &&
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((tor2_pci_ids[x].device == PCI_ANY_ID) ||
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(tor2_pci_ids[x].device == deviceid))) {
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*variant = (char *)tor2_pci_ids[x].driver_data;
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return 1;
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}
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if (variant)
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*variant = NULL;
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return 0;
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}
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#endif /* __KERNEL__ */
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#endif /* NEED_PCI_IDS */
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/*
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* PLX PCI9030 PCI Configuration Registers
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*
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* This is not an all-inclusive list, just some interesting ones
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* that we need and that are not standard.
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*
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*/
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#define PLX_PCI_VPD_ADDR 0x4e /* Set address here */
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#define PLX_PCI_VPD_DATA 0x50 /* Read/Write data here */
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#define PLX_LOC_WP_BOUNDARY 0x4e /* Bits 6-0 here */
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#define PLX_LOC_GPIOC 0x54 /* GPIO control register */
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/* The 4 GPIO data bits we are interested in */
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#define LOC_GPIOC_GPIO4 0x4000 /* GPIO4 data */
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#define LOC_GPIOC_GPIO5 0x20000 /* GPIO5 data */
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#define LOC_GPIOC_GPIO6 0x100000 /* GPIO6 data */
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#define LOC_GPIOC_GPIO7 0x800000 /* GPIO7 data */
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/* define the initialization of the GPIOC register */
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#define LOC_GPIOC_INIT_VALUE 0x2036000 /* GPIO 4&5 in write and
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both high and GPIO 8 in write low */
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/* The defines by what they actually do */
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#define GPIO_WRITE LOC_GPIOC_GPIO4
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#define GPIO_PROGRAM LOC_GPIOC_GPIO5
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#define GPIO_INIT LOC_GPIOC_GPIO6
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#define GPIO_DONE LOC_GPIOC_GPIO7
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#endif /* _TOR2_HW_H */
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