wct4xxp: Refactor t4_serial_setup() to remove t4.globalconfig.
Allows the globalconfig member to be removed from the struct t4 and not carried around for the life of the card. Also holds the reglock a little longer for all the framer writes but I realize the startup of the wct4xxp based cards does not need to be optimized. Signed-off-by: Shaun Ruffell <sruffell@digium.com> Acked-by: Michael Spiceland <mspiceland@digium.com> Acked-by: Russ Meyerriecks <rmeyerriecks@digium.com> git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@10250 a0bf4364-ded3-4de4-8d8a-66a801d63aff
This commit is contained in:
Shaun Ruffell
parent
955641b52c
commit
e14f3fa541
@ -323,7 +323,6 @@ struct t4 {
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unsigned int intcount;
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int num; /* Which card we are */
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int t1e1; /* T1/E1 select pins */
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int globalconfig; /* Whether global setup has been done */
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int syncsrc; /* active sync source */
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struct t4_span *tspans[4]; /* Individual spans */
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int numspans; /* Number of spans on the card */
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@ -1886,65 +1885,102 @@ static void init_spans(struct t4 *wc)
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wc->lastindex = 0;
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}
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static void t4_serial_setup(struct t4 *wc, int unit)
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/**
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* t4_serial_setup - Setup serial parameters and system interface.
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* @wc: The card to configure.
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*
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*/
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static void t4_serial_setup(struct t4 *wc)
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{
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if (!wc->globalconfig) {
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wc->globalconfig = 1;
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if (debug)
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dev_info(&wc->dev->dev, "TE%dXXP: Setting up global "
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"serial parameters\n", wc->numspans);
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t4_framer_out(wc, 0, 0x85, 0xe0); /* GPC1: Multiplex mode enabled, FSC is output, active low, RCLK from channel 0 */
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t4_framer_out(wc, 0, 0x08, 0x01); /* IPC: Interrupt push/pull active low */
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unsigned long flags;
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unsigned int unit;
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/* Global clocks (8.192 Mhz CLK) */
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t4_framer_out(wc, 0, 0x92, 0x00);
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t4_framer_out(wc, 0, 0x93, 0x18);
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t4_framer_out(wc, 0, 0x94, 0xfb);
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t4_framer_out(wc, 0, 0x95, 0x0b);
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t4_framer_out(wc, 0, 0x96, 0x00);
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t4_framer_out(wc, 0, 0x97, 0x0b);
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t4_framer_out(wc, 0, 0x98, 0xdb);
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t4_framer_out(wc, 0, 0x99, 0xdf);
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if (debug) {
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dev_info(&wc->dev->dev,
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"TE%dXXP: Setting up global serial parameters\n",
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wc->numspans);
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}
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spin_lock_irqsave(&wc->reglock, flags);
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/* GPC1: Multiplex mode enabled, FSC is output, active low, RCLK from
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* channel 0 */
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__t4_framer_out(wc, 0, 0x85, 0xe0); /* GPC1: Multiplex mode enabled, FSC is output, active low, RCLK from channel 0 */
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/* IPC: Interrupt push/pull active low */
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__t4_framer_out(wc, 0, 0x08, 0x01);
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/* Global clocks (8.192 Mhz CLK) */
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__t4_framer_out(wc, 0, 0x92, 0x00);
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__t4_framer_out(wc, 0, 0x93, 0x18);
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__t4_framer_out(wc, 0, 0x94, 0xfb);
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__t4_framer_out(wc, 0, 0x95, 0x0b);
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__t4_framer_out(wc, 0, 0x96, 0x00);
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__t4_framer_out(wc, 0, 0x97, 0x0b);
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__t4_framer_out(wc, 0, 0x98, 0xdb);
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__t4_framer_out(wc, 0, 0x99, 0xdf);
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spin_unlock_irqrestore(&wc->reglock, flags);
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for (unit = 0; unit < PORTS_PER_FRAMER; ++unit) {
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spin_lock_irqsave(&wc->reglock, flags);
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/* Configure interrupts */
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t4_framer_out(wc, unit, FRMR_GCR, 0x00); /* GCR: Interrupt on Activation/Deactivation of each */
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/* GCR: Interrupt on Activation/Deactivation of each */
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__t4_framer_out(wc, unit, FRMR_GCR, 0x00);
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/* Configure system interface */
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t4_framer_out(wc, unit, FRMR_SIC1, 0xc2); /* SIC1: 8.192 Mhz clock/bus, double buffer receive / transmit, byte interleaved */
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t4_framer_out(wc, unit, FRMR_SIC2, 0x20 | (unit << 1)); /* SIC2: No FFS, no center receive eliastic buffer, phase */
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t4_framer_out(wc, unit, FRMR_SIC3, 0x04); /* SIC3: Edges for capture */
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t4_framer_out(wc, unit, FRMR_CMR2, 0x00); /* CMR2: We provide sync and clock for tx and rx. */
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if (!has_e1_span(wc)) { /* T1 mode */
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t4_framer_out(wc, unit, FRMR_XC0, 0x03); /* XC0: Normal operation of Sa-bits */
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t4_framer_out(wc, unit, FRMR_XC1, 0x84); /* XC1: 0 offset */
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if (wc->tspans[unit]->linemode == J1)
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t4_framer_out(wc, unit, FRMR_RC0, 0x83); /* RC0: Just shy of 1023 */
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/* SIC1: 8.192 Mhz clock/bus, double buffer receive /
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* transmit, byte interleaved */
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__t4_framer_out(wc, unit, FRMR_SIC1, 0xc2);
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/* SIC2: No FFS, no center receive eliastic buffer, phase */
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__t4_framer_out(wc, unit, FRMR_SIC2, 0x20 | (unit << 1));
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/* SIC3: Edges for capture */
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__t4_framer_out(wc, unit, FRMR_SIC3, 0x04);
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/* CMR2: We provide sync and clock for tx and rx. */
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__t4_framer_out(wc, unit, FRMR_CMR2, 0x00);
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if (!has_e1_span(wc)) { /* T1/J1 mode */
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__t4_framer_out(wc, unit, FRMR_XC0, 0x03);
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__t4_framer_out(wc, unit, FRMR_XC1, 0x84);
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if (J1 == wc->tspans[unit]->linemode)
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__t4_framer_out(wc, unit, FRMR_RC0, 0x83);
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else
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t4_framer_out(wc, unit, FRMR_RC0, 0x03); /* RC0: Just shy of 1023 */
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t4_framer_out(wc, unit, FRMR_RC1, 0x84); /* RC1: The rest of RC0 */
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__t4_framer_out(wc, unit, FRMR_RC0, 0x03);
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__t4_framer_out(wc, unit, FRMR_RC1, 0x84);
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} else { /* E1 mode */
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t4_framer_out(wc, unit, FRMR_XC0, 0x00); /* XC0: Normal operation of Sa-bits */
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t4_framer_out(wc, unit, FRMR_XC1, 0x04); /* XC1: 0 offset */
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t4_framer_out(wc, unit, FRMR_RC0, 0x04); /* RC0: Just shy of 1023 */
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t4_framer_out(wc, unit, FRMR_RC1, 0x04); /* RC1: The rest of RC0 */
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__t4_framer_out(wc, unit, FRMR_XC0, 0x00);
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__t4_framer_out(wc, unit, FRMR_XC1, 0x04);
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__t4_framer_out(wc, unit, FRMR_RC0, 0x04);
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__t4_framer_out(wc, unit, FRMR_RC1, 0x04);
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}
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/* Configure ports */
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t4_framer_out(wc, unit, 0x80, 0x00); /* PC1: SPYR/SPYX input on RPA/XPA */
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/* PC1: SPYR/SPYX input on RPA/XPA */
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__t4_framer_out(wc, unit, 0x80, 0x00);
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/* PC2: RMFB/XSIG output/input on RPB/XPB */
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/* PC3: Some unused stuff */
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/* PC4: Some more unused stuff */
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if (wc->falc31) {
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t4_framer_out(wc, unit, 0x81, 0xBB);
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t4_framer_out(wc, unit, 0x82, 0xBB);
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t4_framer_out(wc, unit, 0x83, 0xBB);
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__t4_framer_out(wc, unit, 0x81, 0xBB);
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__t4_framer_out(wc, unit, 0x82, 0xBB);
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__t4_framer_out(wc, unit, 0x83, 0xBB);
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} else {
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t4_framer_out(wc, unit, 0x81, 0x22);
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t4_framer_out(wc, unit, 0x82, 0x65);
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t4_framer_out(wc, unit, 0x83, 0x35);
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__t4_framer_out(wc, unit, 0x81, 0x22);
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__t4_framer_out(wc, unit, 0x82, 0x65);
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__t4_framer_out(wc, unit, 0x83, 0x35);
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}
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/* PC5: XMFS active low, SCLKR is input, RCLK is output */
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__t4_framer_out(wc, unit, 0x84, 0x01);
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if (debug & DEBUG_MAIN) {
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dev_notice(&wc->dev->dev,
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"Successfully initialized serial bus "
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"for unit %d\n", unit);
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}
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spin_unlock_irqrestore(&wc->reglock, flags);
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}
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t4_framer_out(wc, unit, 0x84, 0x01); /* PC5: XMFS active low, SCLKR is input, RCLK is output */
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if (debug & DEBUG_MAIN)
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dev_notice(&wc->dev->dev, "Successfully initialized serial "
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"bus for unit %d\n", unit);
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}
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static int syncsrc = 0;
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@ -3988,7 +4024,6 @@ static int t4_hardware_init_2(struct t4 *wc)
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static int __devinit t4_launch(struct t4 *wc)
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{
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int x;
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unsigned long flags;
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if (test_bit(DAHDI_FLAGBIT_REGISTERED, &wc->tspans[0]->span.flags))
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return 0;
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@ -3999,9 +4034,7 @@ static int __devinit t4_launch(struct t4 *wc)
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wc->order);
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}
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/* Setup serial parameters and system interface */
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for (x=0;x<PORTS_PER_FRAMER;x++)
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t4_serial_setup(wc, x);
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t4_serial_setup(wc);
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if (dahdi_register(&wc->tspans[0]->span, 0)) {
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dev_err(&wc->dev->dev, "Unable to register span %s\n",
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