wcb4xxp: Protect indirect register writes with sequence lock
A few of the indirect register writes to the A_ST_* indirect registers weren't being protected by any kind of sequence lock. This could lead to potential race conditions of two spans were configured simultaneously. Signed-off-by: Russ Meyerriecks <rmeyerriecks@digium.com>
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@ -1783,16 +1783,19 @@ static void hfc_reset_st(struct b4xxp_span *s)
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else
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b = 0x0c | (6 << V_ST_SMPL_SHIFT);
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b4xxp_setreg8(b4, A_ST_CLK_DLY, b);
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b4xxp_setreg_ra(b4, R_ST_SEL, s->phy_port, A_ST_CLK_DLY, b);
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/* set TE/NT mode, enable B and D channels. */
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b4xxp_setreg8(b4, A_ST_CTRL0, V_B1_EN | V_B2_EN | (s->te_mode ? 0 : V_ST_MD));
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b4xxp_setreg8(b4, A_ST_CTRL1, V_G2_G3_EN | V_E_IGNO);
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b4xxp_setreg8(b4, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
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b4xxp_setreg_ra(b4, R_ST_SEL, s->phy_port, A_ST_CTRL0,
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V_B1_EN | V_B2_EN | (s->te_mode ? 0 : V_ST_MD));
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b4xxp_setreg_ra(b4, R_ST_SEL, s->phy_port, A_ST_CTRL1,
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V_G2_G3_EN | V_E_IGNO);
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b4xxp_setreg_ra(b4, R_ST_SEL, s->phy_port, A_ST_CTRL2,
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V_B1_RX_EN | V_B2_RX_EN);
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/* enable the state machine. */
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b4xxp_setreg8(b4, A_ST_WR_STA, 0x00);
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b4xxp_setreg_ra(b4, R_ST_SEL, s->phy_port, A_ST_WR_STA, 0x00);
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flush_pci();
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udelay(100);
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