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wctc4xxp: Disable read-line and read-line-multiple PCI commands.

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The read-line-multiple command was already disabled on the voicebus cards, which
use the same interface, in commit 4de462c3e0. This
does the same thing for the transcoder card and also disables the read line
command.

I've seen this change directly correlated to problems with the AN983 receiving
packets from the onboard DSP on some platforms.

Internal-Issue-ID: DAHDI-1071
Signed-off-by: Shaun Ruffell <sruffell@digium.com>
Signed-off-by: Russ Meyerriecks <rmeyerriecks@digium.com>
This commit is contained in:
Shaun Ruffell 2014-05-15 13:27:28 -05:00 committed by Russ Meyerriecks
parent 039daca12e
commit 3096ffe955
1 changed files with 21 additions and 10 deletions
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31
drivers/dahdi/wctc4xxp/base.c
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@ -2641,31 +2641,42 @@ static int
wctc4xxp_hardware_init(struct wcdte *wc) wctc4xxp_hardware_init(struct wcdte *wc)
{ {
/* Hardware stuff */ /* Hardware stuff */
enum {
/* Software Reset */
SWR = (1 << 0),
/* Bus Arbitration (1 for priority transmit) */
BAR = (1 << 1),
/* Memory Write Invalidate */
MWI = (1 << 24),
/* Memory Read Line */
MRL = (1 << 23),
/* Descriptor Skip Length */
DSLShift = 2,
/* Cache Alignment */
CALShift = 14,
/* Transmit Auto Pollling */
TAPShift = 17,
};
u32 reg; u32 reg;
unsigned long newjiffies; unsigned long newjiffies;
u8 cache_line_size; u8 cache_line_size;
const u32 DEFAULT_PCI_ACCESS = 0xfff80000; const u32 DEFAULT_PCI_ACCESS = (MWI | (11 << TAPShift));
/* Enable I/O Access */
pci_read_config_dword(wc->pdev, 0x0004, &reg);
reg |= 0x00000007;
pci_write_config_dword(wc->pdev, 0x0004, reg);
if (pci_read_config_byte(wc->pdev, 0x0c, &cache_line_size)) if (pci_read_config_byte(wc->pdev, 0x0c, &cache_line_size))
return -EIO; return -EIO;
switch (cache_line_size) { switch (cache_line_size) {
case 0x08: case 0x08:
reg = DEFAULT_PCI_ACCESS | (0x1 << 14); reg = DEFAULT_PCI_ACCESS | (0x1 << CALShift);
break; break;
case 0x10: case 0x10:
reg = DEFAULT_PCI_ACCESS | (0x2 << 14); reg = DEFAULT_PCI_ACCESS | (0x2 << CALShift);
break; break;
case 0x20: case 0x20:
reg = DEFAULT_PCI_ACCESS | (0x3 << 14); reg = DEFAULT_PCI_ACCESS | (0x3 << CALShift);
break; break;
default: default:
reg = 0xfe584202; reg = (11 << TAPShift);
break; break;
} }