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wcte12xp, wctdm24xxp: '0x0c' -> PCI_CACHE_LINE_SIZE.

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Magic number removal.

Signed-off-by: Shaun Ruffell <sruffell@digium.com>

git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@9327 a0bf4364-ded3-4de4-8d8a-66a801d63aff
This commit is contained in:
Shaun Ruffell 2010-09-14 14:02:35 +00:00
parent 9357a9f953
commit 268b7ea24e
1 changed files with 17 additions and 14 deletions
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31
drivers/dahdi/voicebus/voicebus.c
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@ -243,7 +243,7 @@ vb_initialize_descriptors(struct voicebus *vb, struct voicebus_descriptor_list *
int i; int i;
struct voicebus_descriptor *d; struct voicebus_descriptor *d;
const u32 END_OF_RING = 0x02000000; const u32 END_OF_RING = 0x02000000;
u8 cache_line_size; u8 cacheline_size;
BUG_ON(!dl); BUG_ON(!dl);
@ -253,15 +253,16 @@ vb_initialize_descriptors(struct voicebus *vb, struct voicebus_descriptor_list *
* cache-line sizes that we support. * cache-line sizes that we support.
* *
*/ */
if (pci_read_config_byte(vb->pdev, 0x0c, &cache_line_size)) { if (pci_read_config_byte(vb->pdev, PCI_CACHE_LINE_SIZE,
&cacheline_size)) {
dev_err(&vb->pdev->dev, "Failed read of cache line " dev_err(&vb->pdev->dev, "Failed read of cache line "
"size from PCI configuration space.\n"); "size from PCI configuration space.\n");
return -EIO; return -EIO;
} }
if ((0x08 == cache_line_size) || (0x10 == cache_line_size) || if ((0x08 == cacheline_size) || (0x10 == cacheline_size) ||
(0x20 == cache_line_size)) { (0x20 == cacheline_size)) {
dl->padding = (cache_line_size*sizeof(u32)) - sizeof(*d); dl->padding = (cacheline_size*sizeof(u32)) - sizeof(*d);
} else { } else {
dl->padding = 0; dl->padding = 0;
} }
@ -292,7 +293,7 @@ vb_initialize_tx_descriptors(struct voicebus *vb)
struct voicebus_descriptor *d; struct voicebus_descriptor *d;
struct voicebus_descriptor_list *dl = &vb->txd; struct voicebus_descriptor_list *dl = &vb->txd;
const u32 END_OF_RING = 0x02000000; const u32 END_OF_RING = 0x02000000;
u8 cache_line_size; u8 cacheline_size;
WARN_ON(!dl); WARN_ON(!dl);
WARN_ON((NULL == vb->idle_vbb) || (0 == vb->idle_vbb_dma_addr)); WARN_ON((NULL == vb->idle_vbb) || (0 == vb->idle_vbb_dma_addr));
@ -303,15 +304,16 @@ vb_initialize_tx_descriptors(struct voicebus *vb)
* cache-line sizes that we support. * cache-line sizes that we support.
* *
*/ */
if (pci_read_config_byte(vb->pdev, 0x0c, &cache_line_size)) { if (pci_read_config_byte(vb->pdev, PCI_CACHE_LINE_SIZE,
&cacheline_size)) {
dev_err(&vb->pdev->dev, "Failed read of cache line " dev_err(&vb->pdev->dev, "Failed read of cache line "
"size from PCI configuration space.\n"); "size from PCI configuration space.\n");
return -EIO; return -EIO;
} }
if ((0x08 == cache_line_size) || (0x10 == cache_line_size) || if ((0x08 == cacheline_size) || (0x10 == cacheline_size) ||
(0x20 == cache_line_size)) { (0x20 == cacheline_size)) {
dl->padding = (cache_line_size*sizeof(u32)) - sizeof(*d); dl->padding = (cacheline_size*sizeof(u32)) - sizeof(*d);
} else { } else {
dl->padding = 0; dl->padding = 0;
} }
@ -637,16 +639,17 @@ vb_reset_interface(struct voicebus *vb)
u32 reg; u32 reg;
u32 pci_access; u32 pci_access;
const u32 DEFAULT_PCI_ACCESS = 0xfffc0002; const u32 DEFAULT_PCI_ACCESS = 0xfffc0002;
u8 cache_line_size; u8 cacheline_size;
BUG_ON(in_interrupt()); BUG_ON(in_interrupt());
if (pci_read_config_byte(vb->pdev, 0x0c, &cache_line_size)) { if (pci_read_config_byte(vb->pdev, PCI_CACHE_LINE_SIZE,
&cacheline_size)) {
dev_err(&vb->pdev->dev, "Failed read of cache line " dev_err(&vb->pdev->dev, "Failed read of cache line "
"size from PCI configuration space.\n"); "size from PCI configuration space.\n");
return -EIO; return -EIO;
} }
switch (cache_line_size) { switch (cacheline_size) {
case 0x08: case 0x08:
pci_access = DEFAULT_PCI_ACCESS | (0x1 << 14); pci_access = DEFAULT_PCI_ACCESS | (0x1 << 14);
break; break;
@ -661,7 +664,7 @@ vb_reset_interface(struct voicebus *vb)
dev_warn(&vb->pdev->dev, "Host system set a cache " dev_warn(&vb->pdev->dev, "Host system set a cache "
"size of %d which is not supported. " "size of %d which is not supported. "
"Disabling memory write line and memory " "Disabling memory write line and memory "
"read line.\n", cache_line_size); "read line.\n", cacheline_size);
} }
pci_access = 0xfe584202; pci_access = 0xfe584202;
break; break;