xpp: pri: fix RS1 init in E1 CAS mode
Force some reserved bits to really be 1 in E1 mode (otherwise terrorists will win). (Closes issue DAHLIN-264) Signed-off-by: Oron Peled <oron.peled@xorcom.com> git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@10346 a0bf4364-ded3-4de4-8d8a-66a801d63aff
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@ -1034,6 +1034,17 @@ static int pri_lineconfig(xpd_t *xpd, int lineconfig)
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}
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}
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#endif
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#endif
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if(force_cas) {
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if(force_cas) {
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if(priv->pri_protocol == PRI_PROTO_E1) {
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int rs1 = 0x0B;
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/*
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* Set correct X1-X3 bits in the E1 CAS MFAS
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* They are unused in E1 and should be 1
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*/
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XPD_DBG(GENERAL, xpd, "%s: rs1(0x%02X) = 0x%02X\n",
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__FUNCTION__, REG_RS1_E, rs1);
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write_subunit(xpd, REG_RS1_E, rs1);
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}
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xsp |= REG_XSP_E_CASEN; /* Same as REG_FMR5_T_EIBR for T1 */
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xsp |= REG_XSP_E_CASEN; /* Same as REG_FMR5_T_EIBR for T1 */
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}
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}
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XPD_DBG(GENERAL, xpd, "%s: xsp(0x%02X) = 0x%02X\n", __FUNCTION__, REG_XSP_E, xsp);
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XPD_DBG(GENERAL, xpd, "%s: xsp(0x%02X) = 0x%02X\n", __FUNCTION__, REG_XSP_E, xsp);
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